MediumCVE-2026-0004

    AMD: Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution (CVE-2026-0004)

    Published Last modified Sources: BSI, EUVD, CVE.org, HKCERT

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    What is affected, what to do

    A transient execution vulnerability in some AMD processors may allow an attacker with the ability to execute code on the system to infer data in the L1D cache, potentially resulting in the leakage of sensitive information across privileged boundaries.

    The available sources name no fixed version. Check the vendor guidance in the references below.

    Affected
    • AMD Prozessor = Ryzen..Ryzen
    • open source Xen = 4.20.x..4.20.x
    • open source Xen = 4.19.x..4.19.x
    • open source Xen = 4.18.x..4.18.x
    • open source Xen = 4.17.x..4.17.x
    • open source Xen = 4.21.x..4.21.x
    • AMD Prozessor = EPYC..EPYC
    • AMD Prozessor = Instinct MI300A..Instinct MI300A
    • AMD Radeon = Graphics Driver..Graphics Driver
    • AMD Prozessor = Athlon..Athlon

    Not sure whether and how you are affected? Ask a question about this vulnerability

    Metrics

    5.7

    XIEM Effective CVSS

    Highest available CVSS rating from NVD and vendor data.

    Source: Vendor (CNA), CVSS v4

    5.7

    CVSS v4

    Severity Medium on the scale from 0 to 10.

    Source: BSI, EUVD, CVE.org, HKCERT

    —

    EPSS score

    No value is available for this vulnerability.

    Show all metrics
    Severity
    Medium
    Priority (0–325)

    The priority score is a consolidated metric that condenses several individual signals into a single, action-guiding ranking: technical severity (CVSS), exploitation likelihood (EPSS), known-exploited status (KEV) and the context of the affected asset. The aim is to answer the only truly important question in vulnerability management: what first?

    Read in glossary
    58.50 Methodology
    Exploit maturity

    An exploit is code or a technique that specifically uses a concrete vulnerability to force unintended behaviour — such as executing code or escalating privileges. It is the tool that turns a theoretical flaw into a practical attack.

    Read in glossary
    no public PoC known
    XIEM Effective CVSS

    XIEM® is the tiered managed-security operating model from NEOSEC and a registered trademark of NEOSEC GmbH. It extends classic SIEM — the central collection, normalisation and correlation of security-relevant events — with endpoint forensics, network visibility and deception technology, and consolidates them into three building tiers: Sentry, Orchestrate and Command.

    Read in glossary
    5.7 Methodology
    CVSS v4

    CVSS is the globally established, open standard for assessing the technical severity of a vulnerability on a scale from 0 to 10. It describes how easily a flaw can be exploited and what damage it can cause — but not how likely its actual exploitation is. CVSS and the complementary EPSS deliberately answer different questions.

    Read in glossary
    5.7
    KEV status

    The KEV catalogue is a list maintained by the US authority CISA of vulnerabilities for which active exploitation in the wild has been confirmed. It answers not the question „how severe?“ but „is it already being attacked?“ — thereby sharply prioritising patching.

    Read in glossary
    —
    Published
    CWE

    CWE is a catalogue of typical weakness types in software and hardware — such as flawed input validation, unsafe memory handling or poor authentication. Where a CVE names a concrete vulnerability in a concrete product, a CWE describes the underlying class of defect.

    Read in glossary
    CWE-1421

    Detection rules

    No NEOSEC detection rule is available for this vulnerability yet.

    Classification under NIS2 and CRA

    Rule-based classification from exploitation status and severity. It does not replace a case-by-case assessment.

    NIS2

    NIS2 is EU Directive (EU) 2022/2555 to raise the level of cybersecurity across the Union. It substantially broadens obligations compared with the first NIS directive: more sectors, mandatory risk management, staged reporting duties and personal accountability of senior management.

    Read in glossary
    Handle the vulnerability in regular vulnerability handling under Art. 21(2)(e) NIS2.
    CRA

    The CRA is EU Regulation (EU) 2024/2847 setting horizontal cybersecurity requirements for „products with digital elements“ — from industrial controllers and software to connected consumer devices. For the first time manufacturers must ensure security across the entire product lifecycle, handle vulnerabilities and provide security updates.

    Read in glossary
    From 11.12.2027, Annex I Part II CRA requires manufacturers of affected products with digital elements to handle vulnerabilities without delay and provide security updates.
    ISO/IEC 27001

    ISO/IEC 27001 is the internationally leading standard for an information security management system (ISMS). It describes a risk-based, process-oriented framework to systematically plan, implement, review and improve information security.

    Read in glossary
    Control A.8.8, management of technical vulnerabilities: assess relevance to your systems, plan remediation and keep evidence.

    Description

    A transient execution vulnerability in some AMD processors may allow an attacker with the ability to execute code on the system to infer data in the L1D cache, potentially resulting in the leakage of sensitive information across privileged boundaries.

    Source: BSI WID Portal, BSI CSAF, ENISA EUVD, cvelistv5, NVD (NIST), HKCERT (CC BY 3.0 HK) · HKCERT rating: medium

    Affected products

    The following versions are affected. Older releases of the same product line are also vulnerable unless stated otherwise.

    Affected products
    Affected versionsFixed in
    AMDAMD EPYC™ 8005 Series Processors
    • —
    • —
    AMDAMD EPYC™ 9005 Series Processors
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    AMDAMD EPYC™ Embedded 2005 Series Processors
    • —
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    AMDAMD EPYC™ Embedded 9005 Series Processors
    • —
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    AMDAMD Ryzen™ 9000 Series Desktop Processors
    • —
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    AMDAMD Ryzen™ 9000HX Series Processors
    • —
    • —
    AMDAMD Ryzen™ AI 300 Series Processors
    • —
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    AMDAMD Ryzen™ AI 400 Series Desktop Processors
    • —
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    AMDAMD Ryzen™ AI 400 Series Processors
    • —
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    AMDAMD Ryzen™ AI Max 300 Series Processors
    • —
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    AMDAMD Ryzen™ AI Max 400 Series Processors
    • —
    • —
    AMDAMD Ryzen™ Embedded 9000 Series Processors
    • —
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    AMDAMD Ryzen™ Embedded P100 Series Processors
    • —
    • —
    AMDAMD Ryzen™ Threadripper™ 7000 Processors
    • —
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    AMDAMD Ryzen™ Threadripper™ 9000 Processors
    • —
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    AMDAMD Ryzen™ Threadripper™ PRO 7000 WX-Series Processors
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    AMDAMD Ryzen™ Threadripper™ PRO 9000 WX-Series Processors
    • —
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    AMDAMD Ryzen™ Z1 Series Processors
    • —
    • —
    AMDAMD Ryzen™ Z2 Series Processors Extreme
    • —
    • —
    AMDProzessor
    • Athlon
    • EPYC
    • Instinct MI300A
    • Ryzen
    • —
    • —
    • —
    • —
    AMDRadeon
    • Graphics Driver
    • —
    Open SourceXen
    • 4.18.x
    • 4.21.x
    • 4.19.x
    • 4.20.x
    • 4.17.x
    • —
    • —
    • —
    • —
    • —

    Vendors and products

    Weakness classes (CWE)

    • CWE-1421Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution

      Base

      A processor event may allow transient operations to access architecturally restricted data (for example, in another address space) in a shared microarchitectural structure (for example, a CPU cache), potentially exposing the data over a covert channel.

      Entry at MITRE CWE-1421

    References & sources

    • amd.comen/resources/product-security/bulletin/AMD-SB-3055.htmleuvd
    • amd.comen/resources/product-security/bulletin/AMD-SB-4018.htmleuvd
    • NVD (NIST)vuln/detail/CVE-2026-0004euvd

    Changes to this CVE

    Who changed this CVE and when: NVD (analysis, affected products, CVSS), the CVE publisher (CNA) and additional providers such as CISA (ADP).

    1. Receivedamd.com

      CVSS V4.0: AV:L/AC:H/AT:N/PR:L/UI:N/VC:H/VI:N/VA:N/SC:N/SI:N/SA:N

      Description added or changed

      Show 5 original changes
      Individual changes of this event as published by NVD
      TypeActionBeforeAfter
      Descriptionadded
      —
      A transient execution vulnerability in some AMD processors may allow an attacker with the ability to execute code on the system to infer data in the L1D cache, potentially resulting in the leakage of sensitive information across privileged boundaries.
      CVSSadded
      —
      AV:L/AC:H/AT:N/PR:L/UI:N/VC:H/VI:N/VA:N/SC:N/SI:N/SA:N/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:X
      Affected versions (publisher)added
      —
      New affected value received. <a href="https://github.com/CVEProject/cvelistV5/blob/main/cves/2026/0xxx/CVE-2026-0004.json">CVE-2026-0004</a>
      Referenceadded
      —
      https://www.amd.com/en/resources/product-security/bulletin/AMD-SB-3055.html
      Referenceadded
      —
      https://www.amd.com/en/resources/product-security/bulletin/AMD-SB-4018.html

      Source identifier: psirt@amd.com

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